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Altera_Forum's avatar
Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Motah,

It might be worth doing further teting before commiting yourself.

I mean, you depend on signaltap. I did as well but it could easily mislead due to clock-slip...

I sugget you remove signaltap then test your data in a firmware algorithm, check that you receive what you send directly in firmware and raise a flag if not. Your external loop may be as correct as the local.

Kaz