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Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Iam sorry but I don't agree with the "guarantee". My system would either get the clock right or not depending on power-up. If the phase was wrong it will never recover until I either power-cycled or if I reapplied reset to PLL indicating that that my ref clock was not to blame.

kaz