--- Quote Start ---
Hello,
I have successfully integrated Altera_PLL and Altera_PLL_Reconfig IP in my design. I am able to change the phase of the two clocks that I am interested in. Two questions I have -
1. Is the phase shift cummulative or absolute? Lets say the vco freq is 1GHz, therefore, I should be able to achive phase shifts of 125ps for each step. So lets say I enter a phase shift value of 10 once, and get phase shift of 1250 ps phase shift. Next time when I enter a value of 10, what should I expect to see - phase shift of 2500 ps over the original setting or still 1250 ps?
2. Is there an upper limit to the phase steps? Maybe the max number of phase steps is equivalent to one clock period of the clock that I am changing the phase of?
I appreciate the answers.
Thank you.
Best regards,
--- Quote End ---
I am exploring the altpll, I want to achieve the dynamically phase shift.Now,I am trying to use Nios II, Phase Reconfig Control Register.But I didn't find the way to contrl the device. you use Nios II to control or verilog writted by self ?
question 1： phase shift 2500ps I think; But what fpga device are you using for it? can shift value of 10 once? Actually, the pll reconfig phase one step once.how can you shift 10 once?
question 2: what you think may be right.
Honored Contributor
