Honored ContributorHi,
I'm using a Cyclone III device, in which I'm entering a 24MHz clock into a global clock, wanting to multiply it by 4 to receive a 96MHz. I'm configuring a mega-function to use the PLL. I tested the clock using a frequency measurement equipment: At the input it had a 3ppm and the output had a 300ppm. How come the output had such a bad accuracy? Should it not have a better Accuracy? How can I improve it? Thanks.
Honored ContributorI'm not sure you can improve it. Unfortunately, the PLL Specifications (page 1-15 of the cyclone iii device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf)) don't make for very good reading. They state some, relatively, high figures for jitter that the device may add or cause.
Cheers, AlexHonored ContributorIf you refer to clock jitter, please report your results completely. ppm isn't a usual jitter quantity. If you mean something else, please clarify.
The output of FPGA PLLs (same with microprocessor PLLs) doesn't show particularly low jitter. That's no problem in usual digital applications, but you won't drive a RF ADC with a FPGA PLL if phase noise matters.
