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Honored Contributor
Honored ContributorPLL performnce
Hi, I'm using a Cyclone III device, in which I'm entering a 24MHz clock into a global clock, wanting to multiply it by 4 to receive a 96MHz. I'm configuring a mega-function to use the PLL. ...
Altera_ForumHonored Contributor
Honored ContributorIf you refer to clock jitter, please report your results completely. ppm isn't a usual jitter quantity. If you mean something else, please clarify.
The output of FPGA PLLs (same with microprocessor PLLs) doesn't show particularly low jitter. That's no problem in usual digital applications, but you won't drive a RF ADC with a FPGA PLL if phase noise matters.
