--- Quote Start ---
I have seen that there can be timing problems when not using a dedicated PLL output pin as a clock output but I'm hoping to try and generate a 33MHz output without having to redesign the hardware.
--- Quote End ---
"Timing problems" means slightly increased timing uncertainty and jitter. But it will always correctly transmit the PLL clock.
You don't show the PLL parameters, but provided they are correct, which isn't a big thing for a 48 to 66 MHz converting PLL, the design should work.
Can you tell about the design enviroment? Is it a development kit or a custom designed board? In the latter case, there may be a problem of not providing a clean PLL input clock or other design problems that cause PLL unlock. Monitoring the PLL lock output can help to identify problems of this kind.
Honored Contributor
