Altera_ForumHonored Contributor14 years agoPLL output square wave distorted I am testing PLL output from an old Stratix board. The PLL has an onboard 80MHz crystal as input clock. However at > 60 MHz, the PLL output is not as square as I wish with ripple and 50mv u...Show More
Recent DiscussionsCan you Validate MAX10 Date and Lot Code?HDMI example design errors with Agilex 7MAX10 RSU upgrade succeeds, but device boots Factory image instead of ApplicationVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0carry chain tdc