PLL operating range

question is pretty generic, not related to a specific device. i know PLL frequency range is wide however with a given setup it's pretty narrow and the worse thing is that the PLL may eventually lock onto a multiple frequency of the input. for example say you want to implement an input that accepts input frequencies say from 25 to 100 MHz and PLL is used to multiply this by a given factor (for panel link it's 7). in this case it seems to me the only way is to have a reference crystal to measure input frequency and reprogram PLL parameters accordingly which is a bit complex to do and adds latency in the lock acquisition process.