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Have you tried to reduce your VCO settings, to see if you can get any output?
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Primary Clock 50 MHz
PLL1_Multiplier1 1
PLL1_Divider1 100
PLL1_Multiplier2 1
PLL1_Divider2 25
PLL1_Multiplier3 1
PLL1_Divider3 50
PLL1_Multiplier4 2
PLL1_Divider4 25
PLL2_Multiplier1 1
PLL2_Divider1 25
PLL2_Multiplier2 4
PLL2_Divider2 25
PLL2_Multiplier3 2
PLL2_Divider3 25
PLL2_Multiplier4 8
PLL2_Divider4 25
PLL3_Multiplier1 4
PLL3_Divider1 1
With these settings, all 3 PLLs are working. However, these frequencies are not desirable for my design.
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Also try to observe the PLL source clock on a output or through signal tap directly.
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I have a couple of test GPIO that I connect signals to for inspection. These go to probe sockets on the board for easy measurements.
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If you have to much noise on the PLL supplies, they will have difficulties locking, or may loose lock.
If you don't have the source clock, you will never lock.
My guess would be a wiring error on the board, or needing more analog PLL supply filtering.
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For the most part the power and clock are similar to the DE0_Nano board. I have a single 50mhz clock (
http://www.digikey.com/product-detail/en/asflmb-50.000mhz-ly-t/535-11033-1-nd/2624500) that feeds all 3 PLLs.
I also use the same method for power supply filtering as what is used on the DE0Nano board: I have a 1.2V SMPS with a large range of bypass caps that go into a ferrite bead with more bypass caps which goes into the PLL supply pins. If it is the power, I could do a 1.2V SMPS for VCCINT and a 1.2V LDO for the PLL... I'll try measuring the ripple on VCC_PLL on both boards and see if that could be it.
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