PLL "normal" compensation mode in Cyclone V devices does not work as expected

My answer got obviously killed. So let me try again, this time in prose only in the hope that this will get through. Here is how "normal" mode should work. You have a reference input pin. This signal is put through the PLL at the output of the PLL you have a feedback output and a (regular) clock output pin. For this discussion the feedback output and the clock output have exactly the same frequency. Now the feedback output will be routed through a global clock network and from this network back to the feedback input pin of the PLL. The job of the PLL is to keep the feedback input aligned to the input reference pin. Now if you route the (regular) clock output through another global clock network, the arrival time at (all) the internal registers should be around the same as the arrival time at the feedback input pin of the PLL; this is what global clock networks provide: A very similar delay to all endpoints. Of course this match will not be 100%, but it will be very close. The result is, that the following signals should all be very closely aligned: Reference input pin should be aligned to feedback input pin (that's what the PLL provides), feedback input pin should be aligned to the regular clock signal as it arrives on the internal register clock inputs (that's what the global clock networks provide). So in summary, the reference input pin should be aligned to the signal as it appears on the clock inputs of the internal registers. That's how the PLL should compensate for the delay incurred by the global clock network. Now referring back to the designs I posted: The Cyclone 1 design exactly provides that; for the Cyclone 1 design TimeQuest reports a delay of very close to 0 from the reference input clock pin to the internal registers for the design for fast and slow corners (the delay simply stays very close to 0). The same is absolutely NOT true for the Cyclone V design; here TimeQuest reports a huge delay from the reference input pin to the clock pins of the internal registers; even worse TimeQuest reports hugely different delay for the fast and slow corner; that in turn means the PLL does not really seem to compensate anything useful. And in turn you have a huge uncertainty how your I/O timings will work out, making Cyclone V devices unusable for any high speed parallel interface :-(.