PLL "normal" compensation mode in Cyclone V devices does not work as expected

You are right about the term "Normal". Apologies but my doubts are still valid if I am not missing some points.

The first diagram is just example when clock at register is indeed aligned with pll reference clock. It is an example case as stated on the diagram.

PLL output can lag or advance relatively and this could make testing your way inconclusive.

Moreover, I don't understand your view of "normal", how can a single PLL compensate for any delays to any registers yet having one clock output...or have I misunderstood the concept of delay compensation.