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Not sure about your testing and conclusion.
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Conclusion: Cyclone V devices do not compensate what they should in "normal" compensation mode.
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PLL normal mode compensates for internal delay of clk from its pin to input register...
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Not really true. Maybe you mean "source synchronous compensation mode" ?
Plase see my very first extracted screenshot from the Cyclone 5 manual. "normal" mode means the reference clock at the input pin should be in phase with the clock as it arrives on internal registers (not ONLY input registers).
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...I understand you can tap the scope on pins but you can't on io registers.
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True.
But I can measure the difference between a pin driven by an I/O register, which is clocked directly from the clock pin and a pin driven by an I/O register clocked by a PLL (in "normal" compensation mode).
This gives me an idea how much the PLL is compensating (the pin driven by the I/O register, which is clocked by the PLL should toggle earlier than the pin driven by the I/O register clocked directly by the clock pin).
Result: Cyclone V PLLs do not really compensate anything (TimeQuest says the difference is minimal, measurements show that the difference is higher than TimeQuest thinks, but still quite small.)
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