--- Quote Start ---
It seems Altera does not allow to post anything longer; at least with chromium, the forum software just completely ripped my post apart.
So here is a very short summary:Cyclone V PLLs do not really support "normal" compensation mode; it seems the PLL does not compensate much.
This is especially bad because the clock to output delay has a very wide (4.640 ns) window in which output data might toggle, making any high speed parallel interface very hard to implement
This is rather depressing, because Cyclone 1 devices DO NOT have this problem.
I attach two designs I used to test this; measurements were done with an oscilloscope to verify real life timings
Result: TimeQuest is correct, the Cyclone V devices do not seem to offer any useful compensation of external clocks :-(
--- Quote End ---
Not sure about your testing and conclusion.
PLL normal mode compensates for internal delay of clk from its pin to input register so that it appears at same relationship to data at io register as that at pins.
I understand you can tap the scope on pins but you can't on io registers.
Honored Contributor
