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Honored Contributor
Honored ContributorPLL generation problem
Hi! I have a problem in realizing a PLL. I need a PLL that (with a 50 MHz in input) gives me 3 different clocks: CKSYS,CKPBWR,PCLK. The first have no shift from the clock source. CKPBWR must...
Altera_ForumHonored Contributor
Honored ContributorI have the same problem (same warnings), but what I found is:
After a compilation with Design Space Explorer I modified the phase of two generated clocks in two PLLs. Then I ran Analysis&Synthesis and the Fitter, started TimeQuest and generated a new .sdc-File with my own .sdc-File-Template. My Template defines all clocks in the design and derives the generated clocks (well it did before the compilation with DSE). But now the TimeQuest Analyzer generates me a .sdc-File with the old Values of the PLLs. And when I modify the generated clocks to match the implemented PLLs, Quartus only tells me that Warning. (With expected: <old value>, found: <new value>) Any Idea?
