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Honored Contributor
Honored ContributorPLL generation problem
Hi! I have a problem in realizing a PLL. I need a PLL that (with a 50 MHz in input) gives me 3 different clocks: CKSYS,CKPBWR,PCLK. The first have no shift from the clock source. CKPBWR must...
Altera_ForumHonored Contributor
Honored ContributorHi,
those are TimeQuest messages, IIRC. The constraints in the .SDC file don't match the settings in your PLL compoment. You need to 1. constrain the input clock with "create_clock". 2. use "derive_pll_clocks" to constrain the PLL outputs
