PLL Dynamic Reconfiguration for Stratix III

Hello,

I managed to implement it and used ALTPLL_RECONFIG; my target device was a Stratix III but I had a different frequency range (40MHz -> 65 MHz). I followed AN 454 as example but developed my own state machine to give a reset to the PLL after it locked.

I also used some logic to test the frequency (that board had another clock that was considered "safe" and was used for some built-in tests) and, if necessary, retrigger the reconfiguration.

I did it with Quartus II 9.0 and I had problems with the simulation: the result was not identical to physical device (service request suggestion was to use the Advanced Parameters Configuration).