PLL clock switchover with automatic derivation of PLL clocks is not working

Sorry for the late answer. I've been at home with the flu since last week...

I'm quite sure my base clock constraints are correct. Here they are:

create_clock -name {clk0} 	-period 100.000 -waveform { 0.000 50.000 } 
create_clock -name {clk1} 	-period 100.000 -waveform { 0.000 50.000 } 

Nevertheless I tried what happens without them but with the -create_base_clocks option. The result is still the same. But now, according to the "clock summary" report, Timequest does not even know my base clocks.

After this I disabled the clock switchover option of the PLL and adapted its instantiation in my HDL accordingly. No other changes. Synthesized. Works. Base clock is known and PLL clocks also.

So what I know so far is:

• It works for a single clock and for two clock sources if I write all constraints by hand. Base clocks, PLL input and output clocks and clock groups.

• It works for a single clock if I use the derive_pll_clocks command intead of constraining it by hand. Using -create_base_clocks option has no influence.

• It does not work for two clock sources if I use the derive_pll_clocks command intead of constraining it by hand. Using -create_base_clocks option has no influence.

So far, so bad...