Forum Discussion

fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PLL - variable frequency input, constant output (Max10)

Hello everybody, I would like to connect the RGMII ethernet phy to Max10 device. The phy can output clock and data at 25MHz or 125 MHz (depending in the ethernet datarate), and i would like that my ...
fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Great, thank you for your suggestion, this seems feasible :)

Just one more question: it may turn out that the constant 125MHz clock is a bit too high for my design. Is there a simple way to divide it without the PLL or should i drive the clock signal through some external discrete flipflop on the pcb?

Regards

HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi,

If at all the available PLL is not at all used in your design, you can use it to generate lower frequency from 125MHz system clock.

Otherwise, the idea is to try to use counter logic to divide the clock and see whether it will work or not. I am not sure whether any issue ( compilation warnings/errors) will appear when we use counter to derive the clock.

With Regards,

HPB