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fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PLL - variable frequency input, constant output (Max10)

Hello everybody, I would like to connect the RGMII ethernet phy to Max10 device. The phy can output clock and data at 25MHz or 125 MHz (depending in the ethernet datarate), and i would like that my ...
fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you for your reply.

There is a constant 125MHz clock source available, but the problem is that the Max10 in U169 package has only one PLL, so i cannot use two clock sources ...or is there a way to clock the system with a second clock source without the PLL?

So the only option would be is to have two designs (one for 25MHz clock and the other for 125Mhz clock) stored in configuration flash and a watchdog to switch between them?

  • HBhat2's avatar
    HBhat2
    Icon for Contributor rankContributor
    5 years ago

    Hi,

    There is a constant 125MHz clock source available.

    You can use this clock as the constant clock. You don't need PLL to use this clock. PLL is required only when we need to have some clock synthesis / derive different frequency. otherwise, we can directly use the clock in our design.

    Just define 125MHz as the system clock pin in qsf file and define the frequency of the clock in .sdc file.

    FYI U169 package allows around 4 single ended clocks as it has 4 pairs of clock capable pins ( CLK0p/n, CLK1p/n, CLK2p/n, CLK3p/n) but only one PLL. The 125MHz must be connected any one of the clock capable pins of FPGA so that compilation will not give any error/warning.

    Just a block representation is attached. It shows how we can work with a constant clock freq. using Async FIFO. This is for transmission side. On the receiver side, we need to have one more Async fifo with swapped read & write clock.

    With regards,

    HPB