Occasional Contributor
Occasional ContributorThank you for your suggestion.
I tried to implement this for 125/25MHz, but the ALTPLL Wizard "Cannot implement the requested PLL. Cause: VSO or PFD frequency range exceeded". Also it cannot implement the parameters shown in the example on page 30: "For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control theswitchover using the clkswitch signal. The automatic clock sense circuitry cannotmonitor clock input (inclk0 and inclk1) frequencies with a frequency difference ofmore than 20%." Any idea why? I have the manual switch selected.
Asynchronous FIFO would be used for clock domain crossing. But still i have no idea how to generate a constant frequency with single PLL with variable (25/125MHz) input frequency. Can i also make a swith on the output clock - but then it would be a problem because i have to specify the c0 clock for compensation?
Regard
ContributorHi,
At the moment, I am unable to give suggestion on 125/25MH input to ALTPLL. There may some relation/constraint for switchable input frequency range specified .
Regarding Async FIFO, I hope the FPGA platform which you are using is having atleast one more system clock other than clocks generated by RGMII.
Use that system clock to generate the clock with constant frequency. So, RGMII clocks & system clock will be the 2 asynchronous clocks in your design.
With regards,
HPB
