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Hello!
I'm trying to use PLL to increase frequency of my system. I use Quartus 17 and de0-nano-SoC board.
Steps I did:
1. On my IP catalog I chose Altera PLL:
https://screencast.com/t/nshqodhrq 2. Set settings as the following:
https://screencast.com/t/vphamvpt (I have tried to set "Enable locked output port" and "Enable physical output clock parameters" doesn't help)
3. Once qip/sip is generated and added to the library on my top module I do :
module top_module (
input clk
);
reg clk_pll;
reg pll_reset = 0;
newpll testpll (.refclk(clk), .rst(pll_reset), .outclk_0(clk_pll));
....
But the system doesn't work, modules don't receive signals by clk_pll
Please, any suggestions
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Have you got ref clk driven
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