Forum Discussion

LaurieB's avatar
LaurieB
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Platform Designer generic component does not find signals in HDL

I am using Quartus Prime Pro 23.3.0.

I am trying to create a generic component from VHDL. (file attached)

After analyzing the file, I get the error message "The top-level module does not contain any signals." What would cause this?

Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    Tested on 23.2 and 23.4 without any problem. Only 23.3 got the problem where interface and signals don't appear. I'll report this bug to engineering team. In the mean time, can use 23.4 as workaround.


    Thanks,

    Sheng


8 Replies

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,


    Tested on 23.2 and 23.4 without any problem. Only 23.3 got the problem where interface and signals don't appear. I'll report this bug to engineering team. In the mean time, can use 23.4 as workaround.


    Thanks,

    Sheng


  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Is there a reason why you are creating the component starting from a generic component instead of using the Component Editor? Using Component Editor would avoid this.

    The error I think is because for a generic, you have to not only add the HDL code but you have to manually define all the signals and interfaces on the Signals & Interfaces tab. It doesn't automatically create these for you from the code the way the Component Editor does.

    If you have the HDL code, which you do, there's little reason to not use the Component Editor.

  • LaurieB's avatar
    LaurieB
    Icon for New Contributor rankNew Contributor
    2 years ago

    For the record, I get the same error with Component Editor.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hmm. So what does your Signals & Interfaces tab look like?

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        2 years ago

        According to the video, if you analyzed the HDL file, it should have tried to set up the signals and interfaces. If it's blank like this after analysis, then you would need to set them up yourself manually. Not sure why it is empty since your code looks fine, but this is why you're getting the error.