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LaurieB's avatar
LaurieB
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Platform Designer generic component does not find signals in HDL

I am using Quartus Prime Pro 23.3.0. I am trying to create a generic component from VHDL. (file attached) After analyzing the file, I get the error message "The top-level module does not contain a...
Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    Tested on 23.2 and 23.4 without any problem. Only 23.3 got the problem where interface and signals don't appear. I'll report this bug to engineering team. In the mean time, can use 23.4 as workaround.


    Thanks,

    Sheng


sstrell's avatar
sstrell
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2 years ago

Hmm. So what does your Signals & Interfaces tab look like?

  • LaurieB's avatar
    LaurieB
    Icon for New Contributor rankNew Contributor
    2 years ago

    It's empty

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      According to the video, if you analyzed the HDL file, it should have tried to set up the signals and interfaces. If it's blank like this after analysis, then you would need to set them up yourself manually. Not sure why it is empty since your code looks fine, but this is why you're getting the error.