Placement le constraints

I'm not familiar with the Xilinx commands, but placing LEs by hand is not something that most users do for Altera... The placement & routing in the tool will likely do a better job than you can do by hand (except in rare complex cases where some guidance can help with specific parts of the design, but you certainly wouldn't do it for a full design).

There are location assignments you can make for the Fitter, which rely on the node names after synthesis. If you know the node names you can make placement assignments - I think similar to rloc. To help preserve node names through synthesis, you can use the attributes preserve and keep, documented in Help or the Handbook on Altera's web site. To see examples of the assignment syntax, I recommend using the GUI to back-annotate the placement of a sample design (Assignments menu). You can also try using LogicLock regions to constrain a module of your design, you can find info in Help on how to use those assignments.