Pipelined reads in HPS-to-FPGA bridge

Hi guys,

I have an Avalon-MM slave that uses variable-latency pipelined reads, and I wanna use it in an HPS-based system through the HPS-to-FPGA bridge on a Cyclone V device.

The question is:

Do the AXI3-Avalon circuitry correctly deal those pipelined reads by keeping the throughput? or should I use AXI3 from the scratch?

What do you recommend me ?, thanks in advance for your help.

Alex