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Altera_Forum
Honored Contributor
Honored Contributorpin level before configuration
the pin level is high before fpga has configurad,how can i let the pin's level is low when i power on my board
Altera_ForumHonored Contributor
Honored ContributorBy placing a sufficient low dimensioned pull-down resistor.
P.S.: A suitable value, depending on the connected logic standard is 1K to 2.2 K.
