Pid controller simulation result

I am having a code for digital pid controller. I want to see the simulation result using ALTERA.

entity pid is

port(

u_out:out std_logic_vector( 15 downto 0);

e_in:in std_logic_vector(15 downto 0);

clk:in std_logic;

reset:in std_logic);

end pid;

architecture Behavioral of pid is

signal u1: std_logic_vector(15 downto 0);

signal u_prev : std_logic_vector( 15 downto 0);

signal e_prev1: std_logic_vector( 15 downto 0);

signal e_prev2: std_logic_vector( 15 downto 0);

constant k1: std_logic_vector( 6 downto 0 ):="1101011";

constant k2:std_logic_vector( 6 downto 0):="1101000";

constant k3: std_logic_vector( 6 downto 0) :="0000010";

begin

process( clk)

begin

if( clk'event and clk='1') then

if reset ='1' then

u_prev <="0000000000000000";

e_prev1<="0000000000000000";

e_prev2<="0000000000000000";

else

e_prev2<=e_prev1;

e_prev1<=e_in;

u_prev<=u1;

u1<= u_prev + (k1*e_in)+(k2*e_prev2)+(k3*e_prev2);

end if;

end if;

u_out<=u1;

end process;

end Behavioral;

I need an explanation of simulation result...