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Honored Contributor
Honored ContributorPid control algorithm
Please help to trouble shooot thos code for likely errors cos it's not compiling. Then as a beginner to programming I want to know if the programme will compile work as a PID Controller
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all; entity pid is
port
(
-- input ports
clk : in std_logic;
reset : in std_logic;
e_in : in signed ((data_width-15) downto 0);
setpoint : in signed ((data_width-15) downto 0);
variable k0 : std_logic_vector(15 downto 0);
variable k1 : std_logic_vector(15 downto 0);
variable k2 : std_logic_vector(15 downto 0);
-- output ports
u_out : out signed ((data_width-15) downto 0);
);
end entity; architecture behavioral of pid is component dff
port(
q : out signed(15 downto 0); --output connected to the adder
clk :in std_logic; -- clock input
d :in signed(15 downto 0) -- data input from the mcm block.
);
end component; --read from adc value
y <= adc :in signed(15 downto 0);
e_in <= setpoint - y
-- initializations of parameters
signal mcm0,mcm1,mcm2,add_out: signed(15 downto 0);
signal q1,q2,q3 : signed(15 downto 0); -- latching of signals using d flipflop to introduce delay
begin
dff1 : dff port map(q1,clk,u_out);
dff2 : dff port map(q2,clk,e_in);
dff3 : dff port map(q3,clk,e_in);
end
-- storing outputs of the d flipflops
u_prev <= q1;
e_prev(1) <= q2;
e_prev(2) <= q3; --multiple constant multiplications.
mcm0 <= k0*e_in;
mcm1 <= k1*e_prev(1);
mcm2 <= k2*e_prev(2); --adders
add_out1 <= mcm0 + mcm1;
add_out2 <= add_out1 + mcm2;
u_out <= u_prev + add_out2 --an output produced at every positive edge of clock cycle.
process
begin
if(rising_edge(clk)) then
if <reset == 1> then
u_prev <= 0;
e_prev[1] <= 0;
e_prev[2] <= 0;
else
e_prev[2] <= e_prev[1];
e_prev[1] <= e_in;
u_prev <= u_out;
end if;
end if; end process;
end behavioral pid; --vhdl code for the component dff is given below:
library altera; use altera.altera_primitives_components.all; entity dff is
begin
port(
q : out signed(15 downto 0); --output connected to the adder
clk :in std_logic; -- clock input
d :in signed(15 downto 0) -- data input from the mcm block.
);
end dff; architecture behavioral of dff is signal qt : signed(15 downto 0) := (others => '0'); begin q <= qt; process(clk)
begin
if ( rising_edge(clk) ) then
qt <= d;
end if;
end process; end behavioral;
