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In general FPGA PLLs offer phase shift feature meausured in degrees or time with various degrees of step resolution.
zero phase is just one value of phase that = 0
zero phase buffer is the term used for having same clk output at same freq and phase as input and does not need external loop (fbin is only needed if you don't like the internal fpga analogue loop).
If you mean to offset 2.5 ns between input clk and output then apply negative delay of -2.5ns
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thanks a lot.
i designate -2.5ns phase shift when configuring PLL.
the offset has now become to be less than 500ps. due to the step resolution, it can not be improved further.
in fact, there is originally a 2.5ns delay when i left phase shift to 0, which puzzles me much. now i need to designate a negative value (as you say) to compensate it.
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