PFL with S4 and MAXii

Hi,

I am having a similar problem with the PFL (FPP) scheme.

I have a Max II act as the configuration controller, which load configuration data from a flash and configure a Stratix IV FPGA.

(All terminologies I use here are according to the Parallel Flash loader userguide.)

I followed the Parallel Flash loader megafunction user guide to create a project for Max II. Currently, I can see that whenever the fpga_nconfig line generates a low pulse, the fpga_nstatus follows with a low pulse, and the fpga_conf_done goes to low. But nothing happens afterwards, I don't see a fpga_dclk being generated by the MAX II. However, I do see the pfl_clk working properly.

I kept the pfl_nreset input to high at all time.

Can you provide more details on how to debug the PFL megafunction, and give me some hint please?

Cheers,

Han