Hi Pete
And thank you for your reply.
I don't believe that I have this issue cause it happens to work well.
In fact, I believe that I have a timing issue somewhere.
When I stated that the MAXii PFL design does nothing, I meant that, possibly, it has considered that the S4 simply needs nothing.
That was the purpose of my question regarding the sample timing diagram.
I assume that the PFL design monitors the configuration wires and would decide to start or not the cfg cycle.
This is my missing info.
I will start to simulate, but I do not know if this would work as the AN states that one can not.....
Regards
Thomas