Forum Discussion

Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

PFL Mega Function: Setup time Issue

hi all, I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD. As per the datasheet i did all the constraining for the respective signals. From the CPLD design com...
Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hello Alex & GNg,

thank you for the support.

Is it recommended to use some of the optimizing options which is available in Quartus tool to make it work close to 100Mhz?

@GNg, referring to ug_pfl.pdf, table 7 states that pfl_clk "Can be constrained up to the maximum frequency supported by the PFL IP core"'.

but I couldn't find any document which specifies the Fmax of PFL IP.

is there any document which give the reference of the Fmax ( pfl ip )for a series of cpld devices ?

what I meat is ,for example MAX V(part number:5Mxxxxxxxx) can support Fmax of X Mhz .

thanks