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Hi Kaz, thank you for the reply.
I forget to mention one thing last week.
There are two DVB-ASI inputs on this card.
In different compilation results, the transport stream data in the 1st input cannot be decoded more often than the 2nd input. But the RTL code and timing constraints for both inputs are the same.
Regarding to the possible causes you mentioned:
1). io timing: I use oscilloscope to see the timing relation between clock and data in both inputs. I think they are acceptable by the PCIE bridge chip.
2). fpga timing failure or timing passes but wrong constraints/deconstraints or wrong false paths: I have only one negative slack in my design. I'll check this part today.
3). buffers getting underflow/overflow: for the FIFO I used in my design, the overflow flag is never set to 1.
4). reset issue and any inputs being floating: my design now doesn't have a reset pin. So I only declare a reset input signal in my top module and do not assign pin location to this reset input signal.
5). does failure/pass occur per build or per download powerup or per reset? per build
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For a design like that you need reset. It seems you are reliant on powerup values after configuration. Though you can set that to zero project wide (poweup don't care option unchecked) but Altera recommends user reset since they might power up wrong due to the uncertainty of time an external clock arrives.
You can apply reset to your control signals at least. Data path does not need reset unless you read its value for control purpose. buffers need reset to get ready. It also provides a test if design works after a reset or fails after it.
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