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Altera_Forum
Honored Contributor
Honored ContributorPCML and LVDS clocks, and fitter placement error
I inherited code for high-speed serial data transfer on the Terasic Cyclone V GX dev board. The 1 Gbps link is done with a GXB_RX block (Cyclone V Transceiver Native PHY IP), and the rx_cdr_refclk p...
Altera_ForumHonored Contributor
Honored ContributorI'll be using xcvrs on both HSMC ports (A and B ). Indeed, I am using the Dev kit linked to in the post above (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf)
As TCWORLD pointed out, the relevant clocks are REFCLK_QL2_P/N and REFCLK_QL3_P/N (from on-board oscillators X3 and X4). Using the ClockControl.exe program that came with the Cyclone V GT example software (examples/board_test_system), I was able to set the clock frequency for both oscillators (X3 and X4) to 125MHz. And my code now compiles successfully. The clock programming via ClockControl.exe is volatile. I'll eventually need to figure out how to make this change stick (if I can't figure out a solution, I'll be back to the forum), but for now I have a way to proceed with the SERDES work. Many thanks for the replies -- it's invaluable to have this online support.
