PCML and LVDS clocks, and fitter placement error

Which HSMC bank are you using? As far as I can tell (guessing which dev kit you have), if you are using HSMC Bank A, then there is a dedicated Reference clock pin (REFCLK_QL2_P/N) which is connected to Oscillator X3. This is a programmable oscillator which is by default 148.5MHz, but can be reconfigured to anywhere between 10MHz and 810MHz, so it may be worth looking in to whether it can be made to do 125MHz. Alternatively, if you are using HSMC Bank B, you have a 100MHz clock available (REFCLK_QL3_P/N) - could you alter your design to use 100MHz reference instead of 125MHz?