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Altera_Forum
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11 years ago

PCML and LVDS clocks, and fitter placement error

I inherited code for high-speed serial data transfer on the Terasic Cyclone V GX dev board. The 1 Gbps link is done with a GXB_RX block (Cyclone V Transceiver Native PHY IP), and the rx_cdr_refclk p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Which HSMC bank are you using? As far as I can tell (guessing which dev kit you have), if you are using HSMC Bank A, then there is a dedicated Reference clock pin (REFCLK_QL2_P/N) which is connected to Oscillator X3. This is a programmable oscillator which is by default 148.5MHz, but can be reconfigured to anywhere between 10MHz and 810MHz, so it may be worth looking in to whether it can be made to do 125MHz. Alternatively, if you are using HSMC Bank B, you have a 100MHz clock available (REFCLK_QL3_P/N) - could you alter your design to use 100MHz reference instead of 125MHz?

Dev Kit Reference Manual: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf