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Altera_Forum
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13 years ago

PCIE Hard IP for for HSMC port

Hi, In Cyclone IVGX development kit (NOT the starter kit) with EP4CGX150DF31, the schematic shows that the PCIE hard ip is available for transceiver block GXBL0 - transceiver channels 0-3 (PCIE x4...
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Altera_Forum
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13 years ago

Hi Hmansor,

I had contacted the altera guys, and i got the following reply.

Q1. Does this mean that i can use pcie hard ip if i wish to initiate PCI express connection via HSMC port B (not the pcie edge connector)?

A1. Technically, you can use the HSMC port B to connect the PCIe. However, by default the XCVR_RX_P and XCVR_RX_N channels of the FPGA are connected to the PCIE_RX_P and PCIE_RX_N signals, while the XCVR_TX_P and XCVR_TX_N channels are connected to the PCIE_TX_P and PCIE_TX_N signals. Also, it is not feasible to use the HSMC port B signals as it is single ended (PCIe signals requires differential signals)

Q2. The user guide also states that HSMC port B only supports single ended signaling. Will that be an issue if i want to use PCIE connection via the HSMC port B?

A2. Yes there will be an issue if using HSMC port B because PCIe requires differential signaling.

Hope this helps. If you have any further doubts, feel free to ask.

Best Regards,

Barron.