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Altera_Forum
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9 years ago

PCIe Hard IP build error

i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! -...
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Altera_Forum
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9 years ago

Section 1-5, P319 of the cyclone v handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf).

--- Quote Start ---

The PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.

--- Quote End ---

According to P31 of the cyclone v pin information (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/5cgxfc7.pdf), Pin R2 of the F31 package corresponds to channel 0 of GXB_L2 and is therefore not supported. Pins N2 and K3 are supported as they correspond to channels 1 and 2.