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Avi_V_888's avatar
Avi_V_888
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4 years ago

PCIe gen 4 - 16 lanes in Agilex: maximum rate

Hi'

I using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:256B) CORE, in Agilex device: AGFB014R24A2E2VR0.

The theoretical rate is: 32GB/sec (of course it is not possible to reach such a rate in reality)

The maximum rate at which I was able to transfer information using DMA is 27.5GB/sec (This is not a limitation of the computer itself).

Is it possible to reach a higher rate?
And if so, what could be the reason I'm not succeeding? (Maybe same configuration in the core)

Thanks

Avi

6 Replies

  • Harris's avatar
    Harris
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    4 years ago

    Hi Avi,

    1, Do you use your own DMA design?

    2, What is the MPS and MRRS setting?

    BR/Harris

    • Avi_V_888's avatar
      Avi_V_888
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      4 years ago

      Hi Harris

      First of all thank you.

      Yes I am using my own DMA, but I see that what prevents me from sending data from the DMA to the PCIe Core is that the Core "ready" signal is drops to zero.

      The MPS (maximum payload size) is: 256 Byte

      I do writeד from the Core to the PC and not readings, means that MRRS is not relevant to me

      • Harris's avatar
        Harris
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        4 years ago

        Hi Avi,

        1, Because there are lot of factors impacting throughput, including 128b/130b encoding in physical layer, acknowledge and flow control update in DLL, packet overhead, payload size, DMA design, etc, the throughput can't get to the theoretical data rate(32GB/s).

        2, I suggest you try MPS 512B. From factory test result, the writing throughput(without reading) can get more than 29GB/s with MPS 512B.

        Thanks

        Harris