PCIE auto negotiation in cyclone V

​Hie Aruna,

Please check my replies to your above questions:

Doesn't PCIE link training and speed and width negotiation happen during the PC boot process? Going back to PCie basics; the link training, speed and width negotiation happens when LTSSM goes through Detect->Polling-->Config-->L0.

This process happens during PC boot process. However, if any properties of the link changes (such as Tx PLL loose lock, Rx signal detect deassertion and others); the link will re-train. It will either go through entire link re-training process (Detect-->Polling-->Config-->L0 or go through recovery for speed and width change.

Then, any idea that how the lane width could change between different FPGA reconfiguration via CVP? As explaine above, when performed CvP, the link re-training will start again from Detect

From you side; it seems enabling CvP causes an issue. I will suggest referring to using CvP in Cyclone V from our user guides below to ensure you are performing CvP correctly.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_cvp.pdf

Regards,

Nathan