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ARaja4's avatar
ARaja4
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7 years ago

PCIE auto negotiation in cyclone V

Hi, I'm trying to make gen2 x4 PCIE link using cyclone V 5CGTFD5C5 FPGA. I'm using a custom board and Intel PCIE gen2 X4 FPGA example design. The problem I'm facing is PCIE link always downgrade to ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

​Hie,

Your LTSSM states show you are able to achieve L0 state. Hence, only certain lanes cannot link up.

My primary suspect will be related to receiver detection on some of the upper lanes. Either lane 2 or 3. The case of with CvP and without CvP shows can achieve uptill x2 but not consistent.

Hence, please check the following:

i. AC coupling caps is range of 75-200nF

ii. Differential OCT (termination) is 100ohms

iii. Lanes are not swaped (p-n)

Regards,

Nathan

  • ARaja4's avatar
    ARaja4
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    7 years ago

    Hi,

    Thanks for the reply. I checked with your suggestions and all of them are correct. Besides, I found that changing PCIE RX lanes IO-standard from 1.5V PCML to LVDS solved the issue mostly. (TX lanes IO-standard had to remain 1.5 PCML since its cannot be changed). Most of the times device enumerated Gen 2 X4, but sometimes it was Gen 2 X1. Interesting fact is that, when I do CVP again (without cold or worm boot PC), It enumerates successfully with Gen2 X4. Doesn't PCIE link training and speed and width negotiation happen during the PC boot process? Then, any idea that how the lane width could change between different FPGA reconfiguration via CVP?

    Thanks,

    Aruna

    • ARaja4's avatar
      ARaja4
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      7 years ago

      By doing the CVP again, I mean disabling the driver in device manager and re-enabling it. It seems re enumerate the PCIE.

      Besides, It occurred to me that disabling both CVP and autonomous PCIE enumeration option fixed the problem. Any information about PCIE lane negotiation issues when CVP is enabled?

      Thanks,

      Aruna