PCIe Address Translation Services ... support for ?

This Forum ( and search engines ... ) seems to be silent on the subject.

I would like to run translated reads / writes from the endpoint and believe it must be supported. I can understand if the Hard IP doesn't have the support

but would expect the Soft IP to ... I guess I need to get the Soft IP users guide to see what it says ...

Below is the URL to the PCISIG information and a summary of what it is.

http://www.pcisig.com/specifications/iov/ats/

"PCI-SIG I/O Virtualization (IOV) Specifications, in conjunction with system virtualization technologies, allow multiple operating systems running simultaneously within a single computer to natively share PCI Express® devices. The Address Translation Services (ATS) specification provides a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O Virtualization."

The attached image indicates bits 2 and 3 in the third byte of a READ/ WRITE ( Address Type, AT bits ) are used to support ATS for reads and writes.

For reads, I would

1. make the the translation request with AT bits = 2'b01, and the read data would be the translated address ( not the read data ).

2. endpoint then caches the translated address and subsequently makes reads with AT bits = 2'b10 using the translated address.

3. PCIe RC passes read request on to IOMMU as translated and the IOMMU bypasses any translation look-up or table-walk using the translated address from the endpoint.

4. Read completion returned as normal.

Does anyone know how I would control the AT bits or if that only achievable with the Soft PCIe IP ?