Honored Contributor
Honored ContributorSome older Altera FPGAs were picky about sequence but Cyclone III does not require any specific power up sequence.
Requirements are just that it's monotonic. Cyclone III needs 1.2V for core, 1.2V and 2.5 for PLLs and then 1.2/1.8/2.5/3.0/3.3V for the I/O banks, depending on your configuration. Any decent switched converter will do, provided it can work with the spec (ie, 1.15 -- 1.25 for VCCINT). Power supply and signal integrity issues depend on the frequencies you'll be operating at and also the I/O standards you're using. LVCMOSL I/Os generate much powerfull noise than LVDS. General rules apply. - Use decoupling capacitors and inductors, as much as possible, to filter the power supply lines. Try to use Altera's PDN tool to size them up. - If you're using non-terminated I/Os (ie, LVCMOS) try to keep the traces as short as possible. These I/O standardads don't use matching impedances and reflections are unavoidable. - If you're using terminated I/Os (ie, LVDS) then you can have long traces with good signal integrity, provided you match the line impedance. - In any case, make sure any fast swtiching signal line has a good ground/power plane. Or, if you really really have have to cross a plane discontinuity, put stitching capacitors. Note that JTAG and PROM interface VCCIO as every other pin in bank 1. With Cyclone III, you should add external clamping diodes on the JTAG pins, if you're using 2.5V or higher. The schematics of development boards, (ie, DE-0) are online, and you can use them as starting point. As soon as possible in your PCB design, and definitely before you sign it off for production, you should at least make a mock up project, do the pin assignment and compile it. Then cross check your PCB design with the .pin report file produced by Quartus and the Cyclone III pin connection guidelines.
