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Altera_Forum's avatar
Altera_Forum
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12 years ago

Passive Serial Tri-state

I am designing a Cyclone IV based board with an SPI interface that we would like to use to configure the FPGA with an MCU. We will configure the pins to toggle like Figure 8-16 (Device Handbook Vol ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Notes to Figure 8–16 in Cyclone IV Device Handbook, March:

(1)... (2) ... (3) ...

(4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more convenient.

When using the AS configuration scheme, DCLK is a Cyclone IV device output pin and must not be driven externally.

(5) Do not leave the DATA[0]pin floating after configuration. Drive the DATA[0]pin high or low, whichever is more

convenient.

They didn't say drive staticlly. I think you can connect other pin to these two net directlly.

This should also true for pins nStatus and CONF_DONE.