Passive Serial Tri-state

Figure 8-16 refers to Passive Serial configuration mode. In that mode, DCLK and DATA are inputs, so there is no need for them to tri-state after configuration. The MSEL setting to select Passive Serial configuration mode essentially fixes those pins as inputs.

Notes 4 and 5 on the figure indicate that DCLK and DATA should be driven to a static high or low once you have configured the device. If the MCU SPI interface SCK and MOSI signals are driven to DCLK and DATA on the FPGA, as well as other SPI devices, then I would recommend using a couple of TinyLogic tri-state buffers to isolate the DCLK and DATA inputs from the MCU SPI bus. The tri-state buffers can be enabled for configuration, and then disabled afterwards. Pull-ups or downs on the buffer outputs can be used to hold the DCLK and DATA pins high or low.

The use of buffered DCLK and DATA signals ensures that you have good signal integrity on these FPGA inputs. I'd recommend including a source termination on the output of each of the TinyLogic buffers.

Take a look at this document for some other ideas;

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Cheers,

Dave