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Altera_Forum's avatar
Altera_Forum
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12 years ago

partially assigning values to std_logic_vector array

Hi to all,

I have declared the following type and i have a problem , how should i assigning the x,y, and D std_logic vector (8 bit ) to the pixel ( 24 bit) in the following order pixel ( x(8 bit),y(8 bit),d(8 bit))

TYPE ref_array IS Array (natural Range<>) of std_logic_vector(23 DOWNTO 0);

signal ref_array_xyd : ref_matrix (0 to 25343);

for i IN ref_array_xyd'Range LOOP

ref_array_xyd(i) ( 7 down to 0)<= data;

ref_array_xyd(i) ( 8 down to 15)<= data;

ref_array_xyd(i) ( 16 down to 23)<= data;

END LOOP;

is this right??? please, help

Regards,

sam

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You can also write this as:

     ref_array_xyd <= (others => (datad & datay & datax));

    Be aware that an array of 25344 24 bit std_logic_vectors uses more LEs than you will have in your FPGA, except for the biggest Stratix IV and V ones (which cost a small fortune ...)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Be aware that an array of 25344 24 bit std_logic_vectors uses more LEs than you will have in your FPGA, except for the biggest Stratix IV and V ones (which cost a small fortune ...)

    --- Quote End ---

    In other words, the design isn't synthesizable under practical condiderations.