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Altera_Forum
Honored Contributor
Honored ContributorParallel full case on 32-bit wide data?
Guys, I just ran into a switch-case where you can "case" on non-constant values. For example:
module silly(input clk,
input key,
output is_match,
...
Altera_ForumHonored Contributor
Honored ContributorThere are clearer ways to write the simple compare performed in this code.
The usage of parallel_case seems confusing, because the second case statement is actually overwriting the results of the first. So it's effectively just an inverted priority, no use for this attributes. In addition, I would follow IEEE 1364.1 (Standard for Verilog RTL synthesis) that opts against usage of th full- and parallel_case attributes in synthesized Verilog.
