Parallel full case on 32-bit wide data?

There are clearer ways to write the simple compare performed in this code.

The usage of parallel_case seems confusing, because the second case statement is actually overwriting the results of the first. So it's effectively just an inverted priority, no use for this attributes. In addition, I would follow IEEE 1364.1 (Standard for Verilog RTL synthesis) that opts against usage of th full- and parallel_case attributes in synthesized Verilog.