Parallel Flash for high speed configuration Cyclone IV E device. Can the MAX10 PFL configuration bridge be used? 8 bits or 16 bits Interface to the Cyclone IV? Reference Design?

Hi Dmose2,

Yes, you are correct about PFL can only be use with Quartus programmer via JTAG interface. I checked with my colleague who specialize in Embedded area, it seems that user can consider to use NIOS II with Avalon Tri-State Conduit components in FPGA to access the CFI flash. You can refer to chapter 5.2.6. Nios II Processor Booting from CFI Flash in the Embedded Design handbook for the details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf

Also, you can refer to the Cyclone V dev kit reference manual, schematic and BUP(board portal update) design as reference:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html

Most of the FPGA dev kit come with the BUP(board portal update) design that utilize NIOS II with Avalon Tri-State Conduit components in FPGA. While the PFL in CPLD is use to perform the FPPx16 configuration to Cyclone V.

You can refer to chapter "FPGA Programming from Flash Memory" for some explanation and Figure 2–4. PFL Configuration on the FPGA-CPLD-flash connection from the Cyclone V GT dev kti reference manual:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf

Regards,

Nooraini