Parallel Flash for high speed configuration Cyclone IV E device. Can the MAX10 PFL configuration bridge be used? 8 bits or 16 bits Interface to the Cyclone IV? Reference Design?

Hi ymerm,

Yes, you can use MAX 10 with the PFL IP to perform FPP configuration to any FPGA device. Please refer to the PFL user guide on the PFL IP supporting flash devices:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

Cyclone IV FPP mode only support 8 bits data width. You should refer to the FPP Configuration chapter from the Cyclone IV device handbook to further understand this:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf

The PFL IP (in MAX 10 ) act as the bridge between the flash device and Cyclone IV device to perform:

a) program flash memory devices with the MAX10 device JTAG interface.

b) configuration (e.g. FPP or PS mode) to the Cyclone IV device

You should read the PFL IP user guide to understand usage and settings that you need to perform the FPP mode. Also you can refer to this Configuration walk through from link below which has some useful examples:

https://fpgawiki.intel.com/wiki/Configuration_Walk-Through

You can refer to the Cyclone IV GX development kit schematic as reference in the link below. Even though the Cyclone IV GX development kit is built using PS mode (1 bit data), the difference is the 8 bits data and MSEL pins connection for FPP mode.

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-iv-gx.html

Regards,

Nooraini