Honored Contributor
Honored ContributorRysc, thanks for your suggestion.
Pardon me for my (rookie) question on mucking the clock, as I'm new to FPGA design. I have been doing ASICs and full-custom ICs for over 10 years. In full-custom IC, you always use multi-phase clocks, so that's relatively simple. In ASIC flows, adjusting clock phase by 1/5 for part of the clock tree is not only impractical but also not recommended. Moreover, it's a big NO whenever you mention "multi-cycle path" as it oftentimes creates nightmares. I'm just wondering -- is it common to do all these "highly unrecommended (for ASICs)" in FPGA? FYI, I'm using 3.3V LVTTL/LVCMOS (singled-ended) in Cyclone3 device. Also I can't use source-synchronous on the clock because it's generated off-chip. One thing I can do is to generate a return clock and let the receiver device to sync the signals back to the original clock domain, but that obviously introduces other problems. In my case, the killer is latency. I noticed that some of my output signals have smaller input and/or output delay in the IOOBUFs and thus do meet timing. Is there anything I can do to help Quartus minimize the input/output delays?
