Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi wat_arg,
See the earlier posts about the timing constraints, they are right on. As to changing the time required for a signal to get out of your device, you can only control a few minor things: > make sure the register is moved to an I/O register > make sure you have a strong drive strength - the tCO will be affected by your I/O standard, voltage, and slew rate / drive strength After that you will probably start to look at clock skew, which earlier replies allude to when they talk of using PLLs. good luck